Design for Test (DFT) Engineer

Responsibilities

• Help build and advance the DFT flow including insertion, pattern generation, verification, and signoff
• Architect and implement test access for multi-die packages, including post-package scan-chain access and die-to-die interconnect test
• Implement DFT structures such as scan, compression, boundary scan (JTAG/IEEE 1149.x), and IEEE 1500 core wrapping
• Implement and verify Memory BIST with emphasis on external controllers and shared architectures
• Drive ATPG, fault simulation, coverage closure, and pattern conversion to ATE environments
• Perform DFT verification including scan chain integrity and gate-level simulation
• Support silicon bring-up, debug, diagnosis, and yield/failure analysis
• Collaborate with physical design on scan stitching, timing, and power-aware test

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• 7+ years of hands-on DFT engineering on complex digital SoC/ASIC designs
• Expertise in Siemens Tessent (Scan & ATPG, MemoryBIST, BoundaryScan)
• Strong command of scan insertion, ATPG, fault models, and JTAG/IEEE 1500
• Experience with gate-level simulation and scripting (Tcl, Python, or Perl)
• Familiarity with ATE pattern formats (STIL/WGL) and RTL (Verilog/SystemVerilog)

Preferred Qualifications

• Experience with low-power DFT (UPF/CPF, power-aware ATPG)
• Experience with multi-die or advanced-package DFT architectures

About the Company

DensityAI is a silicon engineering company working on leading-edge multi-die packages.