DDR Memory Interface System Validation Lead Engineer

Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs
• Create and develop comprehensive system-level validation environments and test suites
• Perform pre-silicon and post-silicon functional and electrical validation of controllers, PHYs, and high-speed interfaces
• Execute validation plans covering memory initialization, training, read/write functional validation, and stress testing
• Perform timing characterization, compliance checks, and interoperability testing according to JEDEC specifications
• Analyze signal integrity and timing behavior, including eye diagrams, jitter, and timing margins
• Debug complex silicon, firmware, board-level, and system-level issues
• Collaborate with hardware board design teams on high-speed memory channel implementation and routing strategies
• Develop and maintain validation methodologies, automation frameworks, and measurement flows

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field
• 8+ years of industry experience in memory subsystem validation, silicon validation, or high-speed interface validation

About the Company

Altera is the world’s largest pure-play FPGA solutions provider, delivering programmable technologies that help customers innovate across AI, cloud, networking, and edge markets. With over four decades of expertise, Altera provides an end-to-end portfolio including FPGAs, CPLDs, and System on Modules to accelerate innovation globally.