CPU STA/Timing Engineer

Responsibilities

• Drive timing analysis and closure for complex, multi-GHz CPU designs across block, cluster, and full-chip hierarchies.
• Work with CPU microarchitecture, RTL, and DFT teams to define, implement, and validate timing constraints.
• Perform STA for high-performance CPU designs across multiple modes, corners, and scenarios.
• Analyze timing on frequency-critical CPU paths including core, cache, interconnect, and clocking.
• Provide actionable timing feedback to physical design engineers to enable frequency and timing closure.
• Partner with CAD and methodology teams to develop and enhance CPU-specific timing flows.
• Generate and review logic and physical timing ECOs to close setup, hold, noise, and cross-talk violations.

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• 2+ years of Hardware Engineering experience (or Master's with 1+ year, or PhD).
• Expertise in STA and timing closure.
• Knowledge of multi-clock CPU designs.
• Experience with deep sub-micron technology nodes.
• Understanding of standard cell libraries.
• Familiarity with Verilog.

Preferred Qualifications

• MS degree in Electrical Engineering with ~6+ years of hands-on experience in STA and timing closure.
• Strong experience with STA and timing closure for high-performance CPU or processor-class SoCs.
• Expertise in multi-clock, multi-domain CPU designs with aggressive frequency targets.
• Proven experience performing STA on large CPU/SoC designs with multi-scenario and signoff-quality closure.
• Hands-on knowledge of timing ECO techniques and their implementation.
• In-depth knowledge of timing effects such as noise, cross-talk, and OCV/variation.

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.