CPU Physical Design Engineer, Senior

Responsibilities

• Participate in ASIC development with an emphasis on Place and Route implementation, timing closure, low power optimization, and physical verification
• Create design of experiments and perform detailed PPA (Performance, Power, and Area) comparison analysis to improve result quality and tune recipes
• Collaborate closely with RTL design, Synthesis, low power, Thermal, and Power analysis teams to optimize SoC performance
• Develop and implement Place & Route recipes for optimal PPA results
• Tabulate and analyze metrics to drive project direction and quality improvements

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field
• 9+ years of High Performance core Place & Route and ASIC design implementation experience
• Proficiency in scripting languages such as Perl, Tcl, Python, or C++

Preferred Qualifications

• Extensive experience in Place & Route using Foundry Compiler (FC) or Innovus
• Proven experience with complete ASIC flows, including low power and area optimization techniques
• Experience with Static Timing Analysis (STA) using Primetime or Tempus
• Proficiency in constraint generation and validation
• Experience with multiple power domain implementations and complex UPF/CPF definitions
• Experience with formal verification tools such as Formality or Conformal
• Strong problem-solving skills related to ASIC development and debugging
• Knowledge of CPU micro-architecture and critical path analysis
• Experience with high-speed CPU implementation and Clock Tree Implementation techniques

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.