CPU Design Sr Lead Verification Engineer

Responsibilities

• Responsible for power management verification including Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling
• Develop comprehensive test plans in collaboration with CPU design and verification teams
• Execute test plans using simulation and formal verification methodologies
• Write checkers, assertions, and develop stimulus
• Verify power intent using methodologies like UPF
• Validate system use cases with system architects, software teams, and SoC teams
• Enable verification on emulators and FPGA platforms in coordination with emulation teams
• Debug and triage failures in simulation, emulation, and silicon

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering experience
• OR Master's degree with 3+ years of experience
• OR PhD with 2+ years of experience
• Experience in power management verification
• Implementation of assembly and C language embedded firmware
• Proficiency in C/C++, scripting languages, and Verilog/SystemVerilog
• Strong understanding of power management features in CPUs and CPU-based SoCs
• Experience with clock gating, power gating, UPF, DVFS/DCVS, reliability, and throttling

Preferred Qualifications

• Understanding of CPU architectures and micro-architectures
• In-depth knowledge of digital logic design, microprocessors, debug features, and DFT architecture
• Experience with formal verification and assertions
• Knowledge of DFT and structural debug concepts (JTAG, IEEE1500, MBIST, scan dump, memory dump)