Chip Power Estimation Engineer

Responsibilities

• Architecture, development and correlation of power estimation models/tools for NVIDIA's chips
• Help architect and develop power models for use-cases, Idle power and IO power
• Design tools based on these models and their testing methodology/infrastructures
• Correlate and Calibrate the power models using measured silicon data
• Analyze and help decide the chip configuration and process technology options to optimize power/performance
• Help study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs

Requirements

• B.Tech./M.Tech degree
• 2+ years of experience in Power/Performance estimation and optimization
• Strong fundamentals in transistor-level leakage/dynamic characteristics of VLSI circuits
• Familiarity with low power design techniques (multi VT, Clock gating, Power gating, DVFS)
• Strong background in power estimation techniques, flows and algorithms
• Proficiency in Python and object-oriented programming

Preferred Qualifications

• Exposure to lab setup and power measurement equipment (scope/DAQ)
• Experience with power analysis EDA tools such as PTPX/EPS
• Strong communication skills and teamwork abilities

About the Company

NVIDIA is the AI computing company, driving innovation in parallel and visual computing across consumer graphics, self-driving cars, and artificial intelligence.