Chip Lead, Senior Director

Responsibilities

• Own the full technical lifecycle of the product line including architecture, design integration, and validation strategy
• Drive chip development execution from RTL to GDSII ensuring tapeout milestones are met
• Lead development of large-scale chips utilizing 2.5D/3D advanced packaging and chiplet-based architectures
• Drive alignment across all engineering functions including design verification, DFT, and physical design
• Establish scalable processes, documentation, and handoffs to support company growth
• Mentor teams and foster a culture of ownership and technical accountability

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 15+ years of experience in architecture, silicon design, validation, or systems
• Proven track record of developing large-scale chips (300mm²+) through successful tapeout
• Hands-on experience with 2.5D and 3D advanced packaging and chiplet architectures
• Strong understanding of RTL design, design verification, DFT, and physical design flows
• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
• Demonstrated executive leadership of cross-functional technical programs

Preferred Qualifications

• Master's degree in Electrical Engineering or Computer Engineering
• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
• Experience with advanced process nodes (7nm, 5nm, or below)
• Background in power management, clocking architectures, or high-speed analog integration
• Experience operating in fast-growing startups or hyper-scale environments

About the Company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, enabling organizations to unlock the full potential of modern AI through its Intelligent Connectivity Platform.