CAD DV Senior Engineer, Lead

Responsibilities

• Develop, deploy, and support in-house CAD tools and EDA flows related to Design Verification, Low Power, and Functional Safety.
• Engage with Designers, DV teams, and management to develop verification solutions that meet prescribed requirements.
• Drive company-wide consensus on design tools, flows, and methodologies.
• Document design methodologies and provide training on tools and workflows to design teams.
• Collaborate with EDA vendors to improve tools, implement new functionality, and optimize existing methods.

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• 7+ years of industry experience as a Design Verification engineer or in CAD/EDA tools support and development (or 5+ years with a Master's degree).
• Proven experience in IP/SoC level Verification and Verification Methodology.
• Proficiency in Object-Oriented programming using Python, Perl, C, or C++.
• Strong knowledge of Makefile and Shell Scripting.

Preferred Qualifications

• Experience with RTL, Verilog, SystemVerilog, UPF Verification, GLS, Timing Simulations, and PSS (Portable Stimulus).
• Expertise in process automation using Makefile, Shell, PERL, Tcl, or Python scripting.
• Knowledge of DPI (C, C++) regarding simulation tool debugging.
• Experience with Front-end Digital Design and/or Digital Verification methodologies, specifically focusing on digital and Low Power solutions.
• Demonstrated experience with various EDA software, flows, and architectures (e.g., Synopsys, Cadence).
• UNIX knowledge and experience with data-management software.

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.