ASICS Design Verification Engineer

Responsibilities

• Manage the complete verification lifecycle for digital power IPs, from system-level concept to tape out and post-silicon support
• Perform comprehensive pre-silicon test planning and testbench development using SystemVerilog-UVM methodology
• Develop coverage models, assertion models, and implement formal verification through property checking
• Deploy and implement power-aware UPF verification flows and methodologies
• Develop automation tools and scripts to enhance verification efficiency

Requirements

• Bachelor's degree in Engineering, Science, or a closely related field
• 2+ years of professional experience in ASIC design and verification
• Proficiency with SystemVerilog-UVM methodology
• Strong understanding of digital design concepts and RTL languages (Verilog, SystemVerilog, or VHDL)

Preferred Qualifications

• Master's or PhD in Computer Science, Electrical Engineering, or Computer Engineering
• 6+ years of experience in ASIC design and verification tools and techniques
• Extensive experience with computer architecture fundamentals and Object-oriented programming (C/C++)
• Proven track record of developing block-level testbench environments using SystemVerilog
• Experience with Assertion-based Formal Verification and scripting/automation using Python or Perl
• Familiarity with AMBA Bus protocols (AXI, AHB, APB)

About the Company

Qualcomm is a leading technology innovator dedicated to pushing the boundaries of connectivity and data processing. We drive transformation to help create a smarter, connected future through breakthrough technologies and world-class engineering expertise.