ASICS Design Verification Engineer

Responsibilities

• Manage the complete verification lifecycle for digital power IPs, from system-level concept to tape out and post-silicon support
• Perform comprehensive pre-silicon test planning and testbench development using SystemVerilog-UVM
• Develop coverage models, assertion models, and implement formal verification (property checking)
• Deploy and implement power-aware UPF verification flows and methodologies
• Develop automation tools and scripts to improve overall verification efficiency

Requirements

• Bachelor's degree in Engineering, Science, or a closely related field
• 2+ years of experience in ASIC design and verification tools, techniques, and methodologies
• Proficiency with RTL languages and digital design concepts

Preferred Qualifications

• Master's or PhD in Computer Science, Electrical Engineering, or Computer Engineering
• 6+ years of experience in ASIC design and verification
• Extensive experience with SystemVerilog, Verilog, or VHDL
• Strong understanding of computer architecture, object-oriented programming, and C/C++
• Proven experience developing block-level testbench environments using UVM or OVM
• Proficiency in scripting and automation using Python or Perl
• Experience with AMBA Bus protocols (AXI, AHB, APB) and Assertion-Based Formal Verification

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences. We drive communication and data processing transformation to help create a smarter, connected future for all.