ASIC Verification, Senior Staff Engineer

Responsibilities

• Develop verification testplans and functional coverage to ensure robust verification of memory interface IP
• Implement SV/UVM testbench infrastructure and create test cases to verify memory interface training firmware functionality on RTL PHY models
• Collaborate with architecture and implementation teams through technical reviews to ensure project alignment
• Solve complex verification challenges using advanced debugging tools and analytical thinking
• Mentor junior engineers to foster skill development and a collaborative team environment

Requirements

• Expertise in SystemVerilog with hands-on experience in simulation, waveform debugging, assertions, and coverage analysis
• Proficiency in scripting languages for regression and build systems (e.g., Python, Perl, Shell, makefiles)
• Familiarity with Linux development environments and collaborative engineering workflows
• Bachelor’s degree or higher in Electrical or Computer Engineering, or a related field

Preferred Qualifications

• Expertise in UVM (Universal Verification Methodology)
• Knowledge of DDR or memory interface protocols

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and retirement plans

About the Company

Synopsys is a global leader in semiconductor IP and electronic design automation (EDA) solutions. Our IP Group focuses on developing leading-edge interface IP solutions for memory technologies, driving innovation and technological advancement in the semiconductor industry.