
Posted 7 hours ago
ASIC Verification Engineer
AxiadoASIC Verification Engineer
Requirements
8+ years UVM experience, SystemVerilog, C/Assembly, AMBA protocols, Python/Perl, EE/EECS/CS degree
Skills
SystemVerilogASIC
About the role
Responsibilities
- Lead project verification efforts and help develop test plan definitions
- Perform micro-architecture design verification, RTL verification, and documentation
- Execute top-level and block-level functional, performance, and system-level use-case verification
- Support test program development, chip validation, and chip life until production maturity
- Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams
Requirements
- 8+ years of experience in UVM verification and UVM environment development
- Proficiency in test plan definition and testcase development in C, Assembly, or SystemVerilog
- Expertise in RTL level and gate-level simulation verification
- Strong understanding of coverage analysis, performance verification, and use-case verification
- Hands-on experience with AMBA AXI, AHB, and APB protocols
- Experience with interface protocols such as PCIe, USB, Ethernet, DDR, I2C, SPI, or UART
- Experience in functional test vector development and post-silicon bring-up/debug
- Fluency with scripting languages like Perl, Python, or Shell
- Experience with Bitbucket, Jenkins, and JIRA
- BE/BTECH or ME/MTECH degree in EE, EECS, CS, or equivalent
About the Company
Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.
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Axiado · Taipei
