ASIC Timing Engineer

About the Company

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. We are a fully in-person team in Cupertino that values engineering skills and integrates research with engineering.

Responsibilities

• Drive timing analysis and closure of chips at block, cluster, and full chip level
• Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies and create timing constraints
• Ensure timing and power convergence and manage ECO implementation
• Enhance timing convergence flows in partnership with methodology teams
• Contribute to DFT logic understanding and assist with DFT timing closure for various modes like scan and BIST
• Work on timing closure of digital logic/macros in AMS designs/IPs

Requirements

• BS in Electrical or Computer Engineering with 5+ years of experience, or MS with 2+ years of experience in Timing and STA
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), Fishtail, Lint, CDC, and RDC checks
• Expertise in analyzing and fixing timing paths through ECOs, focusing on crosstalk and noise analysis
• In-depth knowledge of RTL to Netlist and industry-standard STA tools
• Familiarity with deep sub-micron process nodes
• Background in domain-specific STA for GPUs, CPUs, DPUs, or SoCs
• Experience in methodology, flow development, and automation

Benefits

• Full medical, dental, and vision packages (100% premium covered for employees, 90% for dependents)
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in the office
• Relocation support for those moving to Cupertino