ASIC Physical Design Staff Engineer at Synopsys - ScoutJobs - The AI-curated global job board
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Synopsys
Posted a day ago

ASIC Physical Design Staff Engineer

SynopsysASIC Physical Design, Staff Engineer

Perks & benefits

Medical InsuranceMobile AllowancePaid Leave

Requirements

B.Tech or M.Tech in Electronics or VLSI, 5+ years ASIC physical implementation experience, Proficiency in Synopsys tools (Design Compiler, ICC2, Fusion Compiler), Strong scripting in Perl, Tcl, and Python, Knowledge of timing constraint development and EM/IR analysis

Skills

ASICVerilog

About the role

Responsibilities

  • Own the complete physical implementation flow from RTL to GDSII for high-performance interface IPs, test chips, and subsystems at advanced nodes
  • Drive synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing using Synopsys tools
  • Perform static timing analysis, EM/IR signoff, and physical verification to ensure designs meet all timing, power, and reliability targets
  • Develop and refine implementation flows and CAD methodologies to improve turnaround time, PPA, and design predictability
  • Interface with IP architects, verification teams, and product engineering to understand design constraints and customer requirements
  • Debug complex timing, power, and physical issues across multi-million gate designs under tape-out pressure
  • Contribute to scripting and automation efforts using Perl, Tcl, and Python to streamline flows

Requirements

  • B.Tech or M.Tech in Electronics, Electronics & Communication, VLSI Design, Microelectronics, or equivalent
  • 5+ years of hands-on experience in ASIC physical implementation from RTL to GDSII at advanced process nodes
  • Deep working knowledge of Synopsys tools including Design Compiler, ICC2, Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk
  • Proven track record of contributing to recent project tape-outs with responsibility for timing closure or physical verification
  • Strong scripting skills in Perl, Tcl, and Python for flow automation and CAD methodology development
  • Solid understanding of timing constraint development, clock tree synthesis, EM/IR analysis, and physical verification flows

Preferred Qualifications

  • Experience with IP subsystem implementation or multi-die integration

Benefits

  • Comprehensive medical and healthcare plans
  • Paid time away including ETO and FTO programs
  • Family support including maternity, paternity, and adoption assistance
  • Employee Stock Purchase Plan (ESPP) with a 15% discount
  • Competitive salaries and retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services to power innovation across automotive, mobile, and data center markets.

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ASIC Physical Design Staff Engineer

Synopsys · Noida

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