ASIC Physical Design Engineer

Responsibilities

• Own RTL-to-GDSII physical implementation for UCIe IP blocks, including synthesis, floorplanning, power grid architecture, placement, and clock tree synthesis.
• Drive sign-off closure at 7nm, 5nm, or 3nm process nodes.
• Close timing across multiple PVT corners and operating modes to meet latency and bandwidth demands for high-speed die-to-die interfaces.
• Execute physical and electrical verification using Synopsys tools to resolve DRC, LVS, ERC violations and mitigate electromigration, IR-drop, and signal integrity issues.
• Design and validate bump and pad ring patterns for die-to-die architectures.
• Build and maintain automation scripts in Python, Tcl, or Perl to streamline back-end flows.

Requirements

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 1 to 3 years of hands-on ASIC physical design experience with proven RTL-to-GDSII ownership.
• Experience with advanced process nodes such as 7nm, 5nm, or 3nm.
• Deep technical expertise in die-to-die interfaces like UCIe, HBM, or high-speed DDR.
• Proficiency with Synopsys physical design tools, including IC Compiler II, Fusion Compiler, PrimeTime, or IC Validator.
• Advanced scripting skills in Tcl, Python, or Shell for automating complex design problems.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away through ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, powering innovation across AI, HPC, and data center markets.