Posted 20 hours ago
ASIC Engineering Design Verification Leader
CiscoASIC Engineering Design Verification Leader
Requirements
8-12 years experience, SystemVerilog, Python, C, UVM
Skills
SystemVerilogPythonC#UVMASIC
About the role
Responsibilities
- Lead ASIC Engineering Design Verification efforts for high-performance silicon projects
- Drive verification strategies using SystemVerilog, Python, C, and UVM
- Oversee the development and execution of comprehensive verification plans
- Collaborate with cross-functional teams to ensure silicon quality and performance
Requirements
- 8-12 years of professional experience in ASIC Design Verification
- Expert-level proficiency in SystemVerilog and UVM
- Strong programming skills in Python and C
- Proven leadership experience in complex silicon verification environments
About the Company
Cisco is a global leader in technology, driving innovation in networking, security, and cloud computing to connect the world.
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Cisco · Pune
