ASIC DTCO, Timing and Technology Engineer

Responsibilities

• Perform DTCO analysis and Spice simulations to evaluate process technology entitlement (PPAY) for advanced SOC products.
• Conduct power and performance validation and STA sign off using PT/PT-SI and Tempus.
• Execute block-level PPA analysis and implementation (RTL to GDS flow) for hard macros using tools like FC Synthesis, FC Place and Route, Genus, and Innovus.
• Collaborate with foundry DTCO teams, EDA partners, CAD teams, and IP teams to drive Fmax optimization and cost improvements.
• Support the bring-up of new advanced process technologies (5nm, 4nm, 2nm and beyond) from PDK to VLSI design.

Requirements

• Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, or integration experience.
• Master's degree with 1+ year of relevant ASIC experience, or a PhD in a related field.
• Expertise in Spice simulations (Hspice, Finesim, PrimeSim, AFS, or Spectre).
• Proficiency in programming languages such as Python, Perl, TCL, Unix shell, or C/C++.
• Strong knowledge of STA sign off processes.

Preferred Qualifications

• Experience with ML modeling.
• Experience working with advanced process nodes (5nm and below).

About the Company

Qualcomm is a global leader in wireless technology, developing products that power the mobile, compute, automotive, and IoT markets. We hire the brightest minds to solve the world's most complex engineering challenges and invent the future of connectivity.