ASIC Digital Verification, Principal Engineer

Responsibilities

• Design and implement verification environments to ensure the correctness of Interface IP protocols
• Create and execute detailed test plans to verify complex ASIC designs
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM
• Collaborate with design and architecture teams to identify and fix bugs
• Perform functional coverage analysis and drive coverage closure
• Mentor and guide junior verification engineers in best practices and methodologies

Requirements

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols such as PCIe, CXL, DDR, or Ethernet
• Proficiency in SystemVerilog and UVM methodologies
• Strong understanding of digital design and verification concepts
• Experience with simulation tools such as VCS, ModelSim, or similar
• Excellent problem-solving skills and strong attention to detail

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Retirement plans and competitive salary

About the Company

Synopsys is a leader in chip design, verification, and IP integration. Our technology is central to the Era of Pervasive Intelligence, driving innovations in fields ranging from self-driving cars to learning machines. We empower the creation of high-performance silicon chips and software content to transform the future through continuous technological innovation.