ASIC Digital Verification Engineer

Responsibilities

• Define and implement self-checking test cases based on functional requirements
• Contribute to the continuous improvement of verification infrastructure components
• Triage regressions, debug RTL and Gate level simulations, and analyze coverage
• Work with diverse local and remote design and verification team members to achieve verification closure

Requirements

• Bachelor's degree with up to 2 years of experience, or a recent Master's degree with no experience
• Knowledge of SystemVerilog and UVM environments for digital verification
• Experience with Synopsys and/or Cadence simulation tools
• Proficiency with System Verilog assertions, functional coverage, and code coverage
• Ability to work in a Unix/Linux operating system environment
• Strong communication skills and the ability to work under minimal supervision

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose to make our lives easier. As a leading expert in embedded processing, we provide scalable and comprehensive semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a diverse team of over 22,000 professionals globally, we design sustainable, power-efficient solutions that help communities thrive.