ASIC Digital Design, Staff Engineer

Responsibilities

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
• Optimize designs to meet timing, power, and area targets across multiple process nodes
• Develop automation for design generation and flow integration
• Collaborate with cross-functional teams to resolve timing and power challenges
• Contribute to design reviews and methodology development

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of ASIC digital design experience with RTL ownership in production silicon
• Expert Verilog proficiency for timing-critical designs
• Strong Perl scripting skills for design automation
• Deep knowledge of synthesis, timing analysis, and power optimization

Preferred Qualifications

• Experience with PHY IP or high-speed interfaces

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Retirement plans and competitive salary packages

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, partnering closely with customers across various industries to maximize R&D productivity.