ASIC Digital Design Staff Engineer

Responsibilities

• Lead verification ownership for critical IP, defining strategy and driving execution with a team of verification engineers.
• Build and evolve subsystem-level UVM testbenches in SystemVerilog, integrating RTL, behavioral models, and protocol checkers.
• Write and debug advanced test scenarios, assertions, and checkers for complex multi-interface designs.
• Define comprehensive verification test plans with clear coverage goals and drive closure to signoff.
• Manage regression suites, perform root cause analysis on simulation failures, and ensure issues are resolved.
• Collaborate with RTL designers and architects to clarify specifications and ensure functional correctness.
• Mentor verification engineers on UVM methodology, debugging techniques, and best practices.

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Computer Science.
• 5+ years of hands-on ASIC or FPGA verification experience.
• Deep expertise in building and architecting UVM-based testbenches using SystemVerilog.
• Proven track record of technically leading verification efforts and driving coverage closure.
• Strong experience with at least two protocols: DDR, HBM, PCIe, UCIe, Ethernet, or UALink.
• Demonstrated ability to write complex assertions, functional coverage models, and debug difficult simulation failures.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive retirement plans and salaries.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across various industries.