ASIC Digital Design, Sr Staff Engineer

Responsibilities

• Lead the complete subsystem lifecycle from requirements gathering and architecture definition to final release.
• Craft subsystem architectures and develop comprehensive functional specifications.
• Define and implement micro-architectures ensuring compliance with best RTL coding practices.
• Drive RTL quality checks, including linting, CDC, and formal verification to ensure bug-free silicon delivery.
• Collaborate with verification, DFT, and physical implementation teams to ensure seamless project execution.
• Integrate and support standard protocols such as PCIe, DDR, UFS, USB, and AMBA.
• Apply low power design methodologies and ensure DFT requirements are met at the architectural level.
• Mentor junior engineers and participate in technical reviews to foster innovation.

Requirements

• Minimum 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects.
• Proficiency with standard protocols including PCIe, DDR, UFS, USB, and AMBA.
• Demonstrated expertise in low power design methodologies and DFT architecture.
• Strong experience with RTL coding (Verilog/SystemVerilog), linting, CDC, and formal verification tools.
• Proven ability to lead cross-functional teams through all project phases, from specification to silicon.
• Solid understanding of the ASIC design flow, including synthesis, timing analysis, and physical implementation.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away through ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys is a global leader in chip design, verification, and IP integration. Our technology is central to the Era of Pervasive Intelligence, driving innovations in industries ranging from self-driving cars to machine learning.