ASIC Digital Design, Sr Staff Engineer

Responsibilities

• Interpret SerDes standards and architecture documents to develop verification environments and regression testcases in MATLAB
• Evaluate and troubleshoot digital and mixed-signal circuits to resolve complex design challenges
• Collaborate with digital, firmware, and analog teams to improve design methodologies and solve verification challenges
• Adapt and debug internal verification environments to replicate challenging scenarios
• Identify and implement process improvements to enhance efficiency in design procedures
• Document verification environments, plans, and procedures to ensure clear knowledge sharing

Requirements

• 6-10 years of hands-on experience in FPGA design and verification, focusing on IP-level functional verification
• Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping
• Strong programming and scripting skills in Python, C/C++, or TCL for test automation and data analytics
• Deep understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization
• Ability to interpret SerDes standards and digital architecture documentation
• Excellent technical documentation and communication skills

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is a global leader in chip design, verification, and IP integration. We drive the innovations that shape the way we live and connect, providing the technology central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.