ASIC Digital Design, Principal Engineer

Responsibilities

• Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols, including UCIe, for automotive and consumer applications
• Write micro-architecture documents that translate functional specifications into implementable design solutions, defining data paths, control logic, and interface behavior
• Own the full design flow from RTL coding in SystemVerilog through synthesis, CDC analysis, formal verification, and static timing closure
• Collaborate with verification teams to define testplans, close coverage gaps, and debug complex corner cases
• Mentor a distributed team of ASIC designers across multiple sites, performing code reviews and guiding architectural decisions
• Interface with customers to clarify specification ambiguities and ensure IP meets real-world integration requirements
• Drive quality processes using Perforce for revision control and Perl or Shell scripting for automation

Requirements

• BSEE or MSEE in Electrical Engineering
• 12+ years of hands-on experience in ASIC digital design and RTL implementation
• Deep expertise in at least one protocol: UCIe, Ethernet, DDR, PCIe, CXL, or USB
• Strong command of Verilog and SystemVerilog
• Experience with high-speed design considerations and advanced EDA tools such as Fusion Compiler or equivalent
• Proficiency with Perforce and scripting languages like Perl or Shell
• Proven experience technically leading and mentoring teams of ASIC designers

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans