ASIC Design Verification Engineer

Responsibilities

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels
• Develop regression strategy, methodology and tools (scripts)
• Define and measure function coverage and close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach junior engineers and drive verification efficiency

Requirements

• MS with 8+ years of relevant experience or PhD with 3+ years of experience in Electrical Engineering, Computer Engineering, or Computer Science
• In-depth knowledge of UVM/OVM, Semiformal Verification, and assertion-based verification
• Extensive experience in building verification infrastructure, test planning, and coverage closure
• Proficient in Verilog, System Verilog, Python, Perl, TCL, Shell scripting, C/C++, and System C
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocols, and RISC-V/ARM or DSP cores
• Experience verifying designs at both RTL level and post-P&R gate level

Preferred Qualifications

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and digital/analog interfaces
• Experience of design verification for high-speed IO such as PCIE and DDR