ASIC Design Verification Engineer at Synopsys - ScoutJobs - The AI-curated global job board
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Synopsys
Posted 9 hours ago

ASIC Design Verification Engineer

SynopsysASIC Design Verification Engineer

Perks & benefits

Medical InsurancePaid LeaveMobile Allowance

Requirements

Bachelor's or Master's in Electronics Engineering or Computer Science, 3+ years experience in Verification IP or SystemVerilog/UVM, Knowledge of AMBA, Flash, I2C, I3C, DFI, or DRAM protocols, Proficiency in coverage-driven verification plans

Skills

SystemVerilogUVM

About the role

Responsibilities

  • Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, Flash, I2C, I3C, DFI, and DRAM
  • Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
  • Code sequences, test scenarios, and checkers to drive coverage-based verification across functional and code coverage dimensions
  • Debug complex simulation failures across multi-layer protocol stacks to identify root causes in VIP logic and customer integration environments
  • Enhance existing VIP products for performance, reusability, and scalability as protocols evolve
  • Support customers during VIP integration and deployment, troubleshooting issues and ensuring successful bring-up
  • Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps

Requirements

  • Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
  • 3+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based test benches
  • Deep working knowledge of at least two industry-standard protocols such as AMBA (AXI, AHB, APB, LTI, LPI), Flash, I2C, I3C, DFI, or DRAM
  • Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
  • Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis
  • Experience debugging complex simulation failures and resolving issues across protocol layers

Preferred Qualifications

  • Experience working directly with customers or field teams during product deployment

Benefits

  • Comprehensive medical and healthcare plans
  • Paid time away including ETO and FTO programs
  • Family support including maternity, paternity, and adoption assistance
  • Employee Stock Purchase Plan (ESPP) with a 15% discount
  • Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, powering innovation across a wide range of industries.

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ASIC Design Verification Engineer

Synopsys · Noida

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