ASIC Design Verification Engineer

Responsibilities

• Manage the complete verification lifecycle for digital power IPs, from system-level concept to tape out and post-silicon support
• Perform comprehensive pre-silicon test planning and testbench development using SystemVerilog-UVM
• Develop coverage models, assertion models, and implement formal verification (property checking)
• Deploy and implement power-aware UPF verification flows and methodologies
• Develop automation tools and scripts to improve overall verification efficiency

Requirements

• Minimum 3 years of Design Verification (DV) experience using UVM or assertion-based verification technologies
• Proven experience verifying complex SOCs or SOC subsystems
• Strong proficiency in SystemVerilog, UVM, C++, and Python
• Experience with DDR memory protocol verification and using memory verification VIPs
• Background in verifying caches and exposure to DDR phy

Preferred Qualifications

• Experience with formal verification and PASIM simulations
• Exposure to firmware or driver development using C++
• Experience with performance and power verification
• History of successful multiple tapeouts from conception through post-silicon debug

About the Company

Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities that transform industries, create jobs, and enrich lives. We hire the brightest minds to transform 5G's potential into world-changing technologies.