ASIC Design Verification Engineer

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate
• Drive constrained-random and directed testing strategies to validate functionality and corner cases
• Run simulations, triage failures, and collaborate with RTL designers to resolve issues
• Implement and maintain functional, code, and assertion coverage for sign-off
• Manage regression testing, simulation farms, and CI pipelines
• Participate in design reviews and microarchitecture discussions

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 3+ years of experience in ASIC/SoC verification
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows
• Proficiency with simulation tools (VCS, Xcelium, Questa) and waveform debug (Verdi, SimVision)
• Experience with test planning, testbench development, and coverage analysis
• Familiarity with scripting languages (Python, Perl, TCL) and Git

Preferred Qualifications

• Experience with UVM-based testbench development and regression management
• Familiarity with developing and integrating reference models
• Understanding of RTL design flows and industry standard interfaces (APB/AHB/AXI)
• Experience in space, telecom, or RF/digital mixed systems

About the Company

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by leading investors, K2 is mass-producing high-power satellite platforms for missions from LEO to deep space.