ASIC Design Verification Engineer

Responsibilities

• Develop comprehensive and reusable verification environments (Testbenches) using UVM
• Define and execute thorough verification plans including feature lists and coverage goals
• Develop constrained-random, directed, and stress tests
• Execute simulations and debug complex functional failures
• Drive functional and code coverage closure to achieve tape-out quality
• Maintain and manage regression suites to optimize simulation efficiency
• Utilize formal verification techniques for critical design properties
• Develop automation scripts in Python or Perl to enhance verification flow

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 3+ years of professional experience in ASIC/SoC design verification
• Strong proficiency in SystemVerilog and UVM
• Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
• Solid understanding of constrained-random verification and coverage analysis
• Excellent analytical and debugging skills

Preferred Qualifications

• Experience verifying high-speed interfaces, SerDes, or protocols like Ethernet and PCIe
• Exposure to forward error correction (FEC) and scrambling techniques
• Knowledge of formal verification tools like Synopsys VC Formal or Cadence JasperGold
• Familiarity with low-power verification techniques
• Experience with Verilog/SystemVerilog for design understanding
• Exposure to physical layer (PHY) or mixed-signal verification concepts

About the Company

Avicena is developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications, aiming to revolutionize High-Performance Computing (HPC) and Cloud computing.