ASIC Design Engineer

Responsibilities

• Help develop the design and implementation of SoCs
• Perform micro-architecture design, RTL coding, synthesis, timing closure, and documentation
• Optimize top-level and block-level performance, bandwidth, and power
• Work with FPGA engineers for early prototyping
• Support test program development, chip validation, and chip life until production maturity
• Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams

Requirements

• 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization
• Proficiency in writing micro-architecture specifications
• Expertise in Verilog and SoC integration
• Understanding of assertions, coverage analysis, RTL synthesis, and timing closure
• Experience with interface protocols (PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART)
• Experience in design bring up and debug on FPGA emulation platforms (HAPS, Veloce)
• Fluency with scripting languages like Perl or Python
• Proven experience with at least one tapeout

Preferred Qualifications

• Silicon bring-up and debug experience
• Experience with repository management tools (Bitbucket, Jenkins) and bug tracking (JIRA)

About the Company

Axiado is building the future of AI powered digital infrastructure, pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience, and real-time platform management.