Applications Engineering Staff Engineer

Responsibilities

• Support customer engagements across the full ASIC design flow, from RTL to GDSII, focusing on physical implementation.
• Debug complex physical design challenges including placement, optimization, clock tree synthesis, routing, and timing closure at advanced nodes.
• Guide customers through advanced methodologies such as AI-driven design techniques and multi-scenario timing closure.
• Work directly with customer design teams to diagnose tool usage issues and recommend flow improvements.
• Deliver technical presentations, training sessions, and design reviews to translate tool capabilities into actionable strategies.
• Collaborate with Synopsys sales, R&D, and product teams to communicate customer feedback and influence product direction.

Requirements

• Bachelor's degree in Electrical Engineering with 7+ years of hands-on ASIC physical design experience, or a Master's degree with 5+ years.
• Deep experience with RTL-to-GDSII implementation flows using industry-standard tools.
• Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler and ICC2.
• Solid understanding of advanced node design challenges (7nm and below), including multi-corner multi-mode timing closure and noise analysis.
• Demonstrated ability to work directly with customers in technical support or applications engineering roles.

Preferred Qualifications

• Experience with Design Compiler for synthesis.
• Familiarity with PrimeTime for static timing analysis.
• Knowledge of clock tree synthesis methodologies including H-Tree and MS-CTS approaches.

Benefits

• Comprehensive range of health, wellness, and financial benefits.
• Total rewards include both monetary and non-monetary offerings.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services.