Applications Engineering, Sr. Static Timing Analysis Staff Engineer

Responsibilities

• Work directly with leading semiconductor companies to resolve complex timing closure and signoff challenges on advanced node designs.
• Debug critical timing issues including setup and hold violations, clock domain crossings, and SI-induced timing failures using PrimeTime.
• Guide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows for 5nm and below process nodes.
• Collaborate with R&D and product engineering teams to identify root causes and drive tool enhancements or methodology improvements.
• Develop reference flows, automation scripts in Tcl and Python, and best practice documentation for customer adoption.
• Deliver technical training sessions, workshops, and live demos to customer design teams.

Requirements

• Bachelor's degree in Electronics and Communication Engineering, plus a Master's degree in VLSI, Embedded Systems, or Communication Systems.
• Strong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff.
• Deep understanding of timing constraints using SDC, MMMC analysis frameworks, and variation-aware methodologies (OCV, AOCV, POCV).
• Proven ability to debug complex timing issues such as clocking problems and signal integrity effects.
• Proficiency in Tcl scripting for tool automation; experience with Python or Perl is a strong plus.
• Experience with advanced node designs at 5nm and below.
• Excellent communication skills with the ability to engage directly with customers and deliver technical solutions.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services to maximize R&D capability and productivity.