Applications Engineering, Sr. Static Timing Analysis Staff Engineer

Responsibilities

• Resolve complex timing closure and signoff challenges for leading semiconductor companies on advanced node designs.
• Debug critical timing issues including setup/hold violations, clock domain crossings, and SI-induced failures using PrimeTime.
• Guide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows for 5nm and below process nodes.
• Collaborate with R&D and product engineering teams to identify root causes and drive tool enhancements.
• Develop automation scripts in Tcl and Python, reference flows, and best practice documentation.
• Deliver technical training sessions, workshops, and live demos to customer design teams.

Requirements

• Bachelor's degree in Electronics and Communication Engineering.
• Master's degree in VLSI, Embedded Systems, or Communication Systems.
• Strong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff.
• Deep understanding of timing constraints using SDC and MMMC analysis frameworks.
• Proficiency in Tcl scripting for tool automation and flow development.
• Experience with advanced node designs at 5nm and below.
• Excellent communication skills with the ability to engage directly with customers to solve technical challenges.

Preferred Qualifications

• Experience with Python or Perl scripting.
• Proven ability to debug complex variability-driven failures and signal integrity effects.

Benefits

• Comprehensive range of health, wellness, and financial benefits.
• Opportunities to work with industry-leading tools and cutting-edge semiconductor technology.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.