Analog/Mixed-Signal PLL Design Engineer, Senior

Responsibilities

• Architecture, design, and development of analog/mixed-signal hard macros for high-speed clocking IP
• Perform custom circuit design in advanced nanometer FinFET and Gate-All-Around (GAA) technology nodes
• Create design specifications and behavioral models in Verilog
• Set up, run, and analyze circuit simulations using SPICE simulators
• Perform quality assurance procedures and silicon characterization analysis
• Deliver hard macros and support customer integration and testing

Requirements

• Master's or PhD in Science, Engineering, or a related field
• Minimum of 5 years of transistor-level analog mixed-signal design experience
• Proven experience with SPICE simulators and schematic capture tools
• Deep knowledge of PLL, DLL, FLL, and VCO design
• Proficiency in full-custom analog layout techniques and extract verification

Preferred Qualifications

• Experience in frequency synthesis design, high-speed wireline SerDes, or DDR applications
• Understanding of signal integrity in high-speed wireline design
• Scripting skills to automate circuit design and verification workflows
• Knowledge of device physics, power distribution networks (PDN), and SoC top-level integration

Benefits

• Competitive salary, stock, and performance-related bonuses
• Comprehensive insurance including Life, Medical, Income, and Travel
• Matching pension scheme and employee stock purchase scheme
• Maternity and paternity leave
• Education assistance and relocation support
• Subsidized memberships for physical and mental well-being

About the Company

Qualcomm is a global leader in wireless technology, developing the chips and software that power the world's most advanced mobile, automotive, IoT, and compute products. Our engineering teams work at the cutting edge of semiconductor technology to solve the most complex challenges in connectivity and computing.