Analog/Mixed-Signal Layout Engineer

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.

Responsibilities

• Design and/or verification of blocks using leading edge methodology and tools
• Work on high-performance compute and networking standards in advanced CMOS process nodes

Requirements

• Pursuing BS or MS in EE/CS or related fields
• Hardware engineering background with an emphasis in VLSI or Computer Architecture
• Hands-on knowledge of RTL design languages including Verilog and System Verilog
• Familiarity with verification methodologies like UVM, functional coverage, and assertions
• Familiarity with scripting languages such as Python or Perl
• Hands-on experience in C/C++

Preferred Qualifications

• Real-world design and/or verification in Verilog/System Verilog
• Knowledge of high-speed interfaces like PCIe, DDR, HBM, or Serdes
• Familiarity with Synopsys EDA tools