Analog/Mixed-Signal IP DDR Design Engineer

Responsibilities

• Architecture, design, and development of high-speed mixed-signal circuits for LPDDR5, LPDDR6, and next-generation LPDDR systems
• Design custom blocks including high-speed Rx/Tx, clock distribution, clocking delay elements (DLL/PLL), reference blocks, and band-gap circuits
• Perform circuit design for next-generation chip-to-chip architectures
• Execute custom schematic capture, SPICE analysis, and exhaustive pre-silicon validation
• Provide post-silicon bringup support and system enablement
• Collaborate with Analog Mask Layout and Physical Design teams to deliver IP on leading-edge FinFET and Gate-All-Around (GAA) technology nodes
• Address Power Delivery, Signal Integrity, and Power Integrity requirements

Requirements

• Master's or Ph.D. in Science, Engineering, or a related field
• 5+ years of transistor-level analog mixed-signal design experience, preferably in high-speed wireline DDR, SerDes, PLL, or similar applications
• Proficiency with SPICE simulators and schematic capture tools
• Hands-on experience designing op-amps, bandgaps, differential amplifiers, VCO, PLL, and DLL
• Experience with high-speed DDR, SerDes, or IO block-level designs (transmitters, receivers, high-speed VGA, CTLE, CDR, etc.)
• Proficiency in full-custom analog layout techniques, including design completion, layout, extraction verification, and sign-off

Preferred Qualifications

• Understanding of signal integrity in high-speed wireline design
• Experience with scripting and GenAI to automate circuit design and verification workflows

About the Company

Qualcomm's Analog Mixed-Signal IP (MSIP) team designs high-speed mixed-signal circuits for DDR and Chip-to-Chip PHY using leading-edge FinFET and GAA process technologies. We focus on delivering low-power, high-speed designs for a wide array of Snapdragon SoC products.