Analog Layout Engineer

Responsibilities

• Independently develop block‑level and IP‑level analog/RF layouts
• Partner with circuit designers and global layout teams to drive designs from concept to tape‑out
• Own floorplanning, placement, routing, and optimization for complex analog and mixed‑signal blocks (SerDes, ADC/DACs, PLLs)
• Lead and support top‑level integration of multiple analog and mixed‑signal blocks within larger SoCs
• Apply expertise in deep sub‑micron and FinFET process technologies, including EM, ESD, and reliability considerations
• Resolve complex DRC, LVS, antenna, and verification issues

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics, or a related field
• 6+ years of hands-on experience in analog and/or RF layout design
• Proven experience with analog floor planning for complex modules like SerDes, ADC/DAC, or PLLs
• Strong understanding of analog layout best practices for deep sub‑micron CMOS and FinFET technologies

About the Company

Capgemini Engineering is a global leader in engineering services, providing R&D and engineering solutions across various industries, from autonomous vehicles to life-saving robotics.