Analog Layout Design Engineer (Intern)

Responsibilities

• Assist senior engineers in the physical layout design of analog and mixed-signal blocks, such as ADCs, DACs, PLLs, and power management circuits
• Perform layout verification tasks including DRC (Design Rule Check), LVS (Layout Versus Schematic), and antenna checks
• Collaborate with circuit designers to optimize layouts for performance, area, and power
• Document layout methodologies and contribute to design reviews
• Participate in the debugging and resolution of layout-related issues
• Learn and apply company design methodologies and quality standards

Requirements

• Currently pursuing a Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field
• Basic understanding of analog circuit theory and semiconductor device physics
• Familiarity with IC layout concepts and design rules
• Strong analytical and problem-solving skills
• Excellent communication and teamwork abilities

Preferred Qualifications

• Exposure to EDA tools such as Cadence Virtuoso or Mentor Graphics Calibre
• Prior internship experience in semiconductor design

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our broad portfolio of products, including FPGAs, CPLDs, and System on Modules, provides the flexibility to accelerate innovation across the globe.