Analog and RF Layout Engineer

Responsibilities

• Lead the physical layout of complex, high-speed analog and RF mixed-signal blocks from concept through tape-out
• Develop and implement block-level and chip-level layouts in advanced CMOS FinFET technologies (7nm and below)
• Partner with analog, RF, and digital designers to ensure layout quality, performance, and manufacturability
• Own floorplanning, block-level routing, and top-level chip assembly activities
• Apply best-in-class layout techniques to address signal integrity, electromigration, and thermal awareness
• Drive layout reviews, verification, and design rule compliance using industry-standard EDA tools
• Mentor junior engineers and promote engineering best practices

Requirements

• 6+ years of experience in Analog and RF IC layout for high-speed applications
• Hands-on experience with advanced FinFET technologies (7nm and below)
• Strong expertise using EDA tools from Cadence, Mentor, or Synopsys
• Proven experience with high-performance blocks such as high-speed transceivers, CMOS drivers, data converters, and PLLs
• Solid understanding of floorplanning, routing, layer generation, and thermal-aware layout practices

Benefits

• Competitive base compensation
• Paid time off including vacation, personal days, and sick leave
• Medical, dental, and vision coverage
• Retirement savings plans (RRSP in Canada)
• Life and disability insurance
• Employee assistance programs

About the Company

Capgemini Engineering is a global leader in engineering services, providing R&D and digital technology expertise across various industries. We help the world’s most innovative companies unleash their potential through cutting-edge solutions in fields ranging from autonomous vehicles to advanced robotics.