O
Posted 9 hours ago
AMS Engineer
OLIXAMS Engineer
Perks & benefits
Education Allowance
Requirements
BS/MS in Electrical Engineering, 5+ years analog/mixed-signal verification experience, Verilog-AMS expertise, SystemVerilog proficiency, Analog-digital co-simulation experience
Skills
VerilogSystemVerilog
About the role
About the Company
OLIX is developing the Decode Accelerator 1 (DX-1), a new paradigm in AI computing designed to bridge the massive infrastructure gap in AI hardware. By utilizing rack-scale co-design of logic, data movement, packaging, optics, and interconnect, OLIX aims to create a step change in system-level performance for the next generation of AI computing.
Responsibilities
- Own the verification strategy and test plan for mixed-signal subsystems from block level to top-level integration
- Define modeling approaches and fidelity tiers using real-number models, Verilog-AMS, or transistor-level co-sim
- Develop and validate analog behavioral models against transistor-level references
- Build self-checking testbenches and reusable verification components for analog/digital interactions
- Drive AMS co-simulation flows and manage performance and runtime trade-offs
- Define functional coverage and assertions targeting analog corner behavior
- Debug and root-cause failures across the analog/digital boundary
- Partner with analog and DSP designers to review specs and translate analog intent into checkable models
- Own block- and subsystem-level verification sign-off for tape-out
- Build and maintain regression infrastructure and flow automation
- Contribute to silicon bring-up and lab correlation
Requirements
- BS/MS in Electrical Engineering or related field
- 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP
- Expertise with Verilog-AMS and real-number modeling (SystemVerilog real / wreal)
- Experience with analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice)
- Proficiency in SystemVerilog and assertion-based verification
- Ability to model analog blocks at appropriate abstraction levels
- Strong debug skills across the analog/digital boundary
- Ability to read analog schematics and specifications
Preferred Qualifications
- Knowledge of high-speed SerDes / wireline architectures (CDR, PLL, CTLE, DFE)
- Experience verifying calibration and adaptation loops
- UVM or constrained-random, metric-driven verification experience
- Scripting skills in Python, TCL, or Make
- Track record of mixed-signal IP sign-off through tape-out
Benefits
- Competitive Salary
- Meaningful stock options
- Annual Living-Local Bonus for residents within 20 minutes of the office
- Employer-contributed retirement plans
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OLIX · Austin
